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by Research Area | Computer Architecture
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2009
[DCNL-CA-2009-404]
Naga Durga Prasad Avirneni, Viswanathan Subramanian, and Arun K. Somani, "Low Overhead Soft
Error Mitigation Techniques for High-Performance and Aggressive Systems,"
To appear in Proc. of DCCS-DSN 2009, June 2009.
[DCNL-CA-2009-403]
Prem Kumar Ramesh, Viswanathan Subramanian, and Arun K. Somani, "Thermal Management in
Reliably Overclocked Systems," Poster Paper, To Appear in Proc. of SELSE 2009
[DCNL-CA-2009-402]
Naga Durga Prasad Avirneni, Viswanathan Subramanian, and Arun K. Somani, "Soft Error Mitigation Schemes
for High Performance and Aggressive Designs," To Appear in Proc. of SELSE 2009
[DCNL-CA-2009-401]
Shubha Kher, Ganesh Subramanian, Premkumar Ramesh, and Arun K. Somani,
"Greedy Dynamic Crossover Management in Hardware Accelerated Genetic Algorithm
Implementations using FPGA," in UKSIM 2009
2008
[DCNL-CA-2008-405]
Viswanathan Subramanian and Arun K. Somani, "Conjoined Pipeline: Enhancing Hardware Reliability and
Performance through Organized Pipeline Redundancy," in 14th IEEE Pacific Rim International Symposium on
Dependable Computing, PRDC '08, pp.9-16, 15-17 Dec. 2008
[DCNL-CA-2008-403]
Viswanathan Subramanian, Naga Durga Prasad Avirneni, and Arun K. Somani, "Conjoined Processor: A Fault
Tolerant High Performance Microprocessor," Poster Paper, in Proc. of SELSE 2008,
Austin, TX, March 2008.
2007
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[DCNL-CA-2007-401]
Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni and Arun K. Somani,
"Superscalar Processor Performance Enhancement Through Reliable
Dynamic Clock Frequency Tuning," in Proc. of DCCS-DSN 2007, June
2007.
[DCNL-CA-2007-701]
T. S. Ganesh, M. T. Frederick, T. S. B.
Sudarshan, and A. K. Somani, "HashChip: A Shared-Resource Multi-Hash
Function Processor Architecture on FPGA,'' in the Integration, Elsevier
VLSI Journal, Vol. 40, Issue 1, Jan. 2007, pp. 11-19.
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2006
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[DCNL-CA-2006-704]
R. Sangireddy and A. K. Somani,
"On-Chip Adaptive Circuits for Fast Media Processing,'' in Proc. of
IEEE Transactions on Circuits and Systems, Vol. 53, Issue 9, Sept. 2006,
pp. 946-950.
[DCNL-CA-2006-408]
T. S. Ganesh, Viswanathan Subramanian,
and Arun K. Somani, " SEU Mitigation Techniques for Microprocessor
Control Logic,'' in Sixth European Dependable Computing Conference,
Coimbra, Portugal, October 2006, pp. 77-86.
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2005
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[DCNL-
CA- 2005-413]
H. Xu and A. K.
Somani, “Partitioned Cache Shadowing for Deep Sub-Micron (DSM)
Regime,” in Proc. of Pacific Rim Dependability Symposium, Chnagsha,
PRC, Dec 2005, pp/ 183-192.
[DCNL-CA-2005-411]
Shubha Kher, Ganesh T.S., and Arun K. Somani, "Dynamic Crossover
Management in Hardware Accelerated Implementations of Genetic
algorithms," ICIS2005, International Conference on Intelligent
Systems, Dec.1-3, 2005, Kualalumpur, Malaysia.
[DCNL-CA-2005-705]
R. Sangireddy, N.
Futamura, Srinivas Aluru, and Arun K. Somani, "Scalable, Memory
Efficient, High-Speed Algorithms for IP Lookups," in IEEE/ACM
Transactions on Networking, Vol.13, Issue 4, August 2005,
pp. 802-812.
This paper is based on an earlier work presented as N. Futamura, R.
Sangireddy, S. Aluru, and A. K. Somani, "Scalable, memory efficient,
high-speed lookup and update algorithms for IP routing,'' in Proc. of
IEEE Computer Communications and Networks (ICCCN) October 2003, pp.
257-263.
[DCNL-CA-2005-406]
M. Mina, R. Weber, A. K Somani, N. VanderHorn, and R. Bahuguna, ``High
Speed Systems Engineering: A new approach in Electrical and Computer
Engineering,'' 2005 ASEE Annual Conference and Exposition, Portland,
Oregon, July 2005.
[DCNL-CA-2005-704]
R. A. Omari, A. K. Somani,
and G. Manimaran, "An adaptive scheme for fault-tolerant scheduling
of soft real-time tasks in multiprocessor systems," Journal of
Parallel and Distributed Computing, Vol. 65, no. 5, pp. 595-608, May
2005.
This paper is based on earlier work presented as "An Adaptive Scheme
for Fault-Tolerant Scheduling of Soft Real-time Tasks in Multiprocessor
Systems,'' in Proceedings of the International Conference on High Performance
Computing, December 2001, pp.68-80.
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2004
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[DCNL-CA-2004-704]
R. Sangireddy, H. Kim and A. K. Somani,
"Low Power High Performance Reconfigurable Computing Cache
Architectures," IEEE/ACM Transactions on Computers, Vol.
53, No.10, Oct.2004.
This paper is based on earlier work presented as "Low-Power
High-Performance Adaptive Computing Architectures for Multimedia
Processing," in Proceedings of HiPC2002, The Ninth Annual
International Conference on High Performance Computing, December 2002, pp.
124-134.
[DCNL-CA-2004-410]
R. Sangireddy and Arun K. Somani,
"Exploiting Quiescent States in Register Lifetime," in
Proceedings of ICCD2004, The IEEE 22nd International Conference on
Computer Design, October 2004, pp. 368-374.
[DCNL-CA-2004-408]
R. Sangireddy, "Register Organization for Enhanced On-chip
Parallelism," in Proceedings of ASAP2004, The IEEE 15th
International Conference on Application-specific Systems, Architectures
and Processors, September 2004, pp. 180-190.
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2003
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[DCNL-CA-2003-415]
R.Sangireddy, H. Kim, and A. K. Somani, "Timing Issues of Operating
Mode Switch in High Performance Reconfigurable Architectures,'' in
Proceedings of HiPC2003, The Tenth Annual International Conference on
High Performance Computing, December 2003.
[DCNL-CA-2003-409]
R. Sangireddy and
A. K. Somani, "Application-Specific Computing with Adaptive Register
File Architectures," in Proceedings of ASAP2003, The IEEE 14th
International Conference on Application-specific Systems, Architectures
and Processors, pp. 183-193, June 2003.
[DCNL-CA-2003-708]
Sonal Pandey, A. K. Somani, and A. Tyagi, "Intermediate processing
protocol for processing within IP-routed networks,'' special issue of
Microprocessor and Microcontrollers Journal, Volume 27, Issue 5-6. June
2003, pp. 285-295.
This paper
is based on earlier work presented as "A Reliable Protocol for
Procesing within IP-Routed Networks,'' in Proc. of IEEE ICCCN 2002,
October 2002, pp. 84-89.
[DCNL-CA-2003-707]
R. Sangireddy and Arun K. Somani,
"High-Speed IP Routing with Binary Decision Diagrams Based Hardware
Address Lookup Engine," in IEEE Journal on Selected Areas in
Communications, IEEE J-SAC, Volume 21, Issue 4, June 2003, pp. 513-521.
This paper is based on earlier work presented as "Binary Decision Diagrams
for Efficient Hardware Implementation of Fast IP Routing Lookups,"
Proceedings of ICCCN2001, Tenth IEEE International Conference on Computer
Communications and Networks, October 2001, pp. 12-17.
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2002
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[DCNL-CA-2002-402]
R. Sangireddy, "Shadow IP Route Caching
for Trusted Internet Routing," in Proceedings of TIW-2002, The
Trusted Internet Workshop, December 2002.
[DCNL-CA-2002-401]
R. Sangireddy, Huesung Kim, and A. K. Somani,
"Timing Configuration Switch in Reconfigurable Functional Cache
Based Architectures," abstract in Proceedings of FPGA2002, Tenth
ACM International Symposium on Field-Programmable Gate Arrays,
February 2002.
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2001
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[DCNL-CA-2001-709]
S. Kim and A. K. Somani, "On-Line
Integrity Monitoring of Microprocessor Control Logic,"
Microelectronics Journal, Volume 32, Issue 12, December 2001, pp.
999-1007.
This paper is based on earlier work presented as "On-Line Integrity Monitoring
of Microprocessor Control Logic," in International
Conference on Computer Design (ICCD): VLSI in Computers and Processors,
Austin, Texas, September, 2001, pp. 314-319.
[DCNL-CA-2001-409]
S. Kim and A. K. Somani, "SSD: An affordable fault-tolerant
architecture for superscalar processors,'' in Proc. of IEEE 2001 Pacific
Rim International Symposium on Dependable Computing (PRDC), December,
2001.
[DCNL-CA-2001-406] [DCNL-FT-2001-406]
S. Kim and A. K. Somani, "An Affordable Transient Fault Tolerance for
Superscalar Processors," Fast Abstract of IEEE DSN-2001, July 2001.
[DCNL-CA-2001-405]
J. B. Nickel and A. K. Somani, "REESE: A Method of Soft Error
Detection in Microprocessors," in Proc. of International Conference
on Dependable Systems and Networks, June 2001.
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2000
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[DCNL-CA-2000-401]
S. Kim and A. K. Somani, "Characterization of an Extended Multimedia
Benchmark on a General Purpose Microprocessor Architecture," DCNL
technical report, 2000.
[DCNL-CA-2000-400]
S. Kim and A. K. Somani, "Run-Time Locality and Stride Prediction
for Small Data Cache Management, " DCNL technical report, 2000
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1999
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[DCNL-CA-1999-704]
S. Kim and A. K. Somani, "An Adptive Write Error Detection Technique
in On-Chip Caches of Multi-Level Caching Systems," Microprocessors
and Microsystems Journal, Vol. 22, No. 9, March 1999.
[DCNL-CA-1999-407]
A. K. Somani and S. Kim, "Area Efficient Architectures for
Information Integrity Checking in Cache Memories," in the
Proceedings of Internation Symposium on Computer Architecture (accepted
26 out of 135 papers), May 1999, pp. 246-256.
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1998
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[DCNL-CA-1998-404]
S. Kim and A. K. Somani, "Low-cost protection codes for on-chip
cache memories," Fast Abstract in conjuection with IEEE FTCS-98,
held in Munich, June 1998.
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1997
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[DCNL-CA-1997-704]
Craig M. Wittenbrink and Arun K. Somani, "Time and Space
Optimal Data Parallel Volume Rendering Using Permutation Warping,"
in Journal of Parallel and Distributed Computig, Volume 46, Number 2,
November 1, 1997, pp. 148-164.
This paper is based on earlier work presented as "Permutation Warping for Data
Parallel Volume Rendering," in Parallel Rendg Symposium,
Visualization `93, San Jose, California, 1993, pages 57-60, color plate
page 110.
[DCNL-CA-1997-701]
Victor Lee, Nghia Lam, Feng Xiao, and Arun K. Somani, "Superscalar
and Superpipelined Microprocessor Design and Simulation: A Senior
Project," in IEEE Transactions on Education, Vol. 40, No. 1,
February 1997, pp. 89-97.
[DCNL-CA-1997-402]
A. K. Somani and K. S. Trivedi, "A Cache Error Propagation
Model," in the Proc. of 1997 Pacific Rim International Symposium on
Fault Tolerant Systems, Teipei, Taiwan, pp. 15-21, December 1997.
[DCNL-CA-1997-401]
A. K. Somani and S. Kim, "Transient Fault Detection in Cache
Memories by Employing a Small Shadow Cache," in Proc. of DCCA-6,
March 1997, pp. 21-46.
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1996
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[DCNL-CA-1996-706]
C. Chen and A. K. Somani, "Architectural Techniques Tradeoff Using
Mean Memory Delay Time," in IEEE Transactions on Computers, Vol. 45,
No. 10, October 1996, PP. 1089-1100.
This
paper is based on earlier work presented as "A Unified Architectural
Tradeoff Methodology," in the Proc. of ISCA 94, Chicago, April 1994,
pp. 348-357.
[DCNL-CA-1996-702]
Craig M. Wittenbrink, A. K. Somani, and C.-H. Chen, "Cache Write
Generate for Parallel Image Processing on Shared Memory
Architectures," in IEEE Transactions on Image Processing, Vol. 5,
No. 7, July 1996, pp. 1204-1208.
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1995
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[DCNL-CA-1995-702]
C. Wittenbrink and A. K. Somani, "2D and 3D Optimal Parallel Image
Warping," Journal of Parallel and Distributed Computing, Vol. 25,
No. 2, pages 197-208, March 1995.
This
paper is based on earlier work presented as "2D and 3D optimal
parallel image wraping," in the Proc.of Seventh International
Parallel Processing Symposium, Newport Beach, CA, April 13-16, 1993,
pp.331-336.
[DCNL-CA-1995-701]
R. M. Haralick, A. K. Somani, C. Wittenbrink, R. Johnson, K. Cooper, L.
G. Shapiro, I. T. Phillips, J. N. Hwang, W. Cheung, Y. H. Yao, C.-H Chen,
L. Yang, B. Daugherty, B. Lorbeski, K. Loving, T. Miller, L. Parkins, and
S. Soos, "Proteus: A Reconfigurable Computational Network for
Computer Vision," Machine Vision and Applications, 1995, Vol. 8 (no.
2), pp. 85-100, February 1995.
This
paper is based on earlier work presented as "Proteus: A
Reconfigurable Computational Network for Computer Vision,"
International Conference on Pattern Recognition 1992, Computer Vision and
Pattern Recognition 1992, March 1992, pp. 43-54 (Judged among the 6 best
papers). This work was also presented in the Proc. of the SPIE, The Intl.
Society for Optical Engineering, Vol. 1659, pp. 54-76, 1992.
[DCNL-CA-1995-405]
D. Fura and A. K. Somani, "Transaction-Level Specification of VHDL
Design Models," in VHDL International Users' Forum, October 1995.
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1994
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[DCNL-CA-1994-406]
D. Fura and A. K. Somani, "Component Interval Semantics and
Efficient Verification of Transaction-Level Circuit Behavior," in T.
Melham and J. Camilleri (eds.), Higher Order Logic Theorem Proving and
its Applications, Lecture Notes in Computer Science, 859,
Springer-Verlag, 1994, pp. 205-220.
[DCNL-CA-1994-404]
C. Chen and A. K. Somani, "A Cache Protocol for Error Detection and
Recovery in Fault-Tolerant Computing Systems," in the Proc. of FTCS
94, Austin, June 1994, pp. 278-287.
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1993
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[DCNL-CA-1993-701]
C. Wittenbrink and A. K. Somani, "Cache Tiling for High-Performance
Morphological Image Processing," in Machine Vision and Applications,
special issue on vision processing architectures, Nov. 1993, pp. 12-22.
This paper is based on earlier work presented as "Cache Tiling for
High-Performance Morphological Image Processing," in the Proc. of
Computer architecture for Vision Processing, France in December 1991, pp.
427-438 (Judged among the 6 best papers).
[DCNL-CA-1993-404]
C. Wittenbrink and A. K. Somani, "Permutation warping for volume
rendering," in the Proc. of the Fifth Annual Western Computer
Graphics Symposium, Silver Star Mountain, British Columbia, 1993
[DCNL-CA-1993-403]
D. Fura, Phillip J. Windley, and A. K. Somani, "Abstraction
Techniques for Modeling Real-World Interface Chips," in J. Joyce and
C. Segar (eds.), Higher Order Logic Theorem Proving and its Applications,
Lecture Notes in Computer Science, 780, Springer-Verlag, 1994, pp.
269-282.
[DCNL-CA-1993-402]
R. M. Haralick, Y. H. Yao, L. G. Shapiro, I. T. Phillips, A. K. Somani,
J. N. Hwang, M. Harrington, C. Wittenbrink, C. H. Chen, X. Liu, S. Chen,
"Proteus Management and Control System," in Proc. of 1993
Computer Architecture and Machine Perception, New Orleans, LA, Dec. 1993,
pp. 101-108.
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1992
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[DCNL-CA-1992-408]
G. Greenwood and A. K. Somani, "A methodology for Mapping Pipelined
Algorithms onto Hypercube Arrays," in the Proc. of 5th IEEE
Conference on Parallel and Distributed Computing, December, 1992, Teipai,
pp. 386-391.
[DCNL-CA-1992-404] [DCNL-FT-1992-404]
C. Chen and A. K. Somani, "Error Detection and Recovery in Fault
Tolerant Processor Systems Using Caches," in the Proc. of 5th Conf.
of ISMM on Parallel and Distributed Systems, October 1992, Pittsburgh,
pp. 388-393.
[DCNL-CA-1992-403]
T. Kanungo, G. Chiou, A. K. Somani, and R.M. Haralick,"Morphological
Image Processing on a Token Passing Pyramid Computer," In the Proc.
of International Conference on pattern Recognition, The Hague,
Netherlands, August 1992.
[DCNL-CA-1992-402]
C. Chen and A. K. Somani, "Effect of Cache Traffic on Shared-Bus
Multiprocessor Systems," in the Proc. of ICPP-92, August 1992,
Chicago, IL, pp I285-I288.
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1991
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[DCNL-CA-1991-402]
[DCNL-CN-1991-402]
A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang,
C. Chen, R. Johnson, and K. Cooper, "Proteus System Architecture and
Organization," in the Proc. of 5th International Parallel Processing
Symposium, June 1991, pp. 287-294.
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1985
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[DCNL-CA-1985-701]
A. K. Somani and V. K. Agarwal, "An Efficient Unsorted VLSI
Dictionary Machine," IEEE Transactions on Computers, Vol. c-34, no.
9, September 1985, pp. 841-852.
This paper
is based on earlier work presented as "An Unsorted Dictionary
Machine," in the Proc. of Canadian VLSI Conference, University of
Waterloo, Waterloo, Canada, October 1983, pp. 80-83, and "An
Efficient VLSI Dictionary Machine," in the Proc. of IEEE Symposium
of Computer Architectures-1984, University of Michigan, Ann Arbor,
U.S.A., June 1984, pp. 142-150.
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